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Apple

ASIC Design Engineer - Cache Controller

28 days ago• Santa Clara, CA

About us

Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.

★ 3.7 out of 5 · 120 reviews

  • Size: 10,000+ employees
  • Industry: Technology: Manufacturing
View company profile ›

Why you should apply for a job to Apple:

  • Ranked as one of the Best Technology Companies in 2020
  • 3.7/5 in overall job satisfaction
  • 3.1/5 in supportive management
  • 66% say women are treated fairly and equally to men
  • 65% would recommend this company to other women
  • 66% say the CEO supports gender diversity

Ratings are based on anonymous reviews by Fairygodboss members. See all reviews ›

Apple is building the world's fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy.

Description

Design and develop hardware for cache subsystem in high performance system on a chip (SoC).

Develop cache micro-architecture based on architecture guidelines and model analysis.

Explore architecture trade-offs in system performance, area, and power consumption.

Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem.

Work on front-end netlist and area/timing analysis of the cache subsystem.

Work with physical design team on the timing closure of the cache subsystem.

Preferred Qualifications

Cache design background including good understanding of different memory organizations and tradeoffs

Experience with multi-processor cache coherence protocols

Knowledge of high-performance coherent memory systems or interconnect architectures

Knowledge of high-performance DRAM controller

M.S in a relevant field.

Minimum Qualifications

3+ years of full time ASIC design experience

memory system development

RTL/micro-architecture definition

PPA (performance/power/area) analysis

B.S. in a relevant field

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 and $277,600, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

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Additional Information

  • Salary: $150,400 – $277,600
  • Posted: 28 days ago
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